--
-- VHDL Architecture Balance.vol_stim.arch
--
-- Created:
--          by - toban963.student (southfork-15.edu.isy.liu.se)
--          at - 18:33:52 10/08/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY vol_stim IS
   PORT( 
      Audio_in_left_v  : OUT    std_logic_vector (23 DOWNTO 0);
      Audio_in_right_v : OUT    std_logic_vector (23 DOWNTO 0)
   );

-- Declarations

END vol_stim ;

--
ARCHITECTURE arch OF vol_stim IS
BEGIN
  
    Audio_in_left_v <= "11111111" & "11111111" & "11111111";
        Audio_in_right_v <= "11111111" & "11111111" & "11111111";
END ARCHITECTURE arch;

